A serial communication system communicates data in reference to a serial communication clock. A plurality of state machines are generally required to support a communication protocol within the serial communication system. To maintain proper sequencing of state machines within the serial communication system which are dependent on the accuracy of the serial communication clock, the serial communication clock is required to be free of extraneous voltage spikes. When an extraneous voltage spike is detected on the serial communication clock during a data transmission, the serial communication system is interrupted and data transmission is repeated.
A known method of detecting extraneous voltage spikes on a serial communication clock involves the use of a circuit known as a voter circuit. The voter circuit will generally have a plurality of connected latches with an output of each latch being connected to a voting logic gate circuit. An input of the voter circuit couples the serial communication clock at a predetermined frequency. The predetermined frequency is generally substantially greater than the serial communication clock. The voting logic gate circuit then determines if the data within the serially connected latches is correct at predetermined time intervals. Problems with the voter circuit include, but are not limited to: a substantial amount of logic required for implementation, the voter circuit is required to operate at higher frequency rates, and a predetermined amount of critical time delay of the serial communication clock exists. The predetermined amount of time delay of the serial communication clock requires that the serially transmitted data also be delayed.
Another approach to assuring the integrity of data communication when an extraneous voltage spike occurs on a serial communication clock is through the use of an analog filter. The analog filter is coupled in series between the serial communication clock and the serial communication system. The analog filter allows only the serial communication clock signal to pass and filters out all other signals. A problem with the analog filter approach is that it is not readily adaptable to a general purpose communication system having a range of operating frequencies for the serial communication clock.
It is therefore desired to maintain proper sequencing of state machines within the serial communication system which are dependent on the integrity of the serial communication clock which operates over a range of frequencies. It is further desired that only a minimum of additional logic circuitry be required to guarantee the system integrity without time delay.